o
    Ñ­jÕX  ã                   @   s”   d Z ddlZddlmZmZmZmZmZmZ ddl	m
Z
mZmZmZmZmZmZmZmZ g d¢ZG dd„ deƒZG dd	„ d	eƒZG d
d„ deƒZdS )z×
    pygments.lexers.hdl
    ~~~~~~~~~~~~~~~~~~~

    Lexers for hardware descriptor languages.

    :copyright: Copyright 2006-present by the Pygments team, see AUTHORS.
    :license: BSD, see LICENSE for details.
é    N)Ú
RegexLexerÚbygroupsÚincludeÚusingÚthisÚwords)	ÚTextÚCommentÚOperatorÚKeywordÚNameÚStringÚNumberÚPunctuationÚ
Whitespace)ÚVerilogLexerÚSystemVerilogLexerÚ	VhdlLexerc                   @   s¾  e Zd ZdZdZddgZdgZdgZdZdZ	dZ
d	ejd
fdefdeejeƒfdejfdejfdefdedfdejfdejfdejfdejfdejfdejfdejfdefdejfdefdefdejfdeeeje ƒfdeeeje ƒd fe!d!d"d#�efe!d$d%d"d&�ejfe!d'd(d"d&�ej"fe!d)d"d#�ej#fd*ej$fd+efd,efgd-ed.fd/ejfd0efdeejeƒfd1efgd2ejfd3ejfd4ejd.fd5ejfd6ejfd7ed.fgd8ejd.fgd9œZ%d:d;„ Z&d<S )=r   z?
    For verilog source code with preprocessor directives.
    ÚverilogÚvz*.vztext/x-verilogz%https://en.wikipedia.org/wiki/Verilogz1.4ú(?:\s|//.*?\n|/[*].*?[*]/)+z^\s*`defineÚmacroú\s+ú(\\)(\n)ú/(\\\n)?/(\n|(.|\n)*?[^\\]\n)ú/(\\\n)?[*](.|\n)*?[*](\\\n)?/ú[{}#@]úL?"Ústringú4L?'(\\.|\\[0-7]{1,3}|\\x[a-fA-F0-9]{1,2}|[^\\\'\n])'ú%(\d+\.\d*|\.\d+|\d+)[eE][+-]?\d+[lL]?ú(\d+\.\d*|\.\d+|\d+[fF])[fF]?z([0-9]+)|(\'h)[0-9a-fA-F]+z([0-9]+)|(\'b)[01]+z([0-9]+)|(\'d)[0-9]+z([0-9]+)|(\'o)[0-7]+z\'[01xz]z\d+[Ll]?ú[~!%^&*+=|?:<>/-]ú[()\[\],.;\']ú`[a-zA-Z_]\w*ú^(\s*)(package)(\s+)ú^(\s*)(import)(\s+)Úimport)qÚalwaysÚalways_combÚ	always_ffÚalways_latchÚandÚassignÚ	automaticÚbeginÚbreakÚbufÚbufif0Úbufif1ÚcaseÚcasexÚcasezÚcmosÚconstÚcontinueÚdeassignÚdefaultÚdefparamÚdisableÚdoÚedgeÚelseÚendÚendcaseÚendfunctionÚendgenerateÚ	endmoduleÚ
endpackageÚendprimitiveÚ
endspecifyÚendtableÚendtaskÚenumÚeventÚfinalÚforÚforceÚforeverÚforkÚfunctionÚgenerateÚgenvarÚhighz0Úhighz1ÚifÚinitialÚinoutÚinputÚintegerÚjoinÚlargeÚ
localparamÚmacromoduleÚmediumÚmoduleÚnandÚnegedgeÚnmosÚnorÚnotÚnotif0Únotif1ÚorÚoutputÚpackedÚ	parameterÚpmosÚposedgeÚ	primitiveÚpull0Úpull1ÚpulldownÚpullupÚrcmosÚrefÚreleaseÚrepeatÚreturnÚrnmosÚrpmosÚrtranÚrtranif0Úrtranif1ÚscalaredÚsignedÚsmallÚspecifyÚ	specparamÚstrengthr   Ústrong0Ústrong1ÚstructÚtableÚtaskÚtranÚtranif0Útranif1ÚtypeÚtypedefÚunsignedÚvarÚvectoredÚvoidÚwaitÚweak0Úweak1ÚwhileÚxnorÚxorú\b©Úsuffix)Ú
accelerateÚautoexpand_vectornetsÚ
celldefineÚdefault_nettyper@   ÚelsifÚendcelldefineÚendifÚ
endprotectÚendprotectedÚexpand_vectornetsÚifdefÚifndefr   ÚnoaccelerateÚnoexpand_vectornetsÚnoremove_gatenamesÚnoremove_netnamesÚnounconnected_driveÚprotectÚ	protectedÚremove_gatenamesÚremove_netnamesÚresetallÚ	timescaleÚunconnected_driveÚundefú`)Úprefixrš   )4ÚbitsÚ
bitstorealÚbitstoshortrealÚcountdriversÚdisplayÚfcloseÚfdisplayÚfinishÚfloorÚfmonitorÚfopenÚfstrobeÚfwriteÚ
getpatternÚhistoryÚincsaverZ   ÚitorÚkeyÚlistÚlogÚmonitorÚ
monitoroffÚ	monitoronÚnokeyÚnologÚprinttimescaleÚrandomÚreadmembÚreadmemhÚrealtimeÚ
realtobitsÚresetÚreset_countÚreset_valueÚrestartÚrtoiÚsaveÚscaleÚscopeÚshortrealtobitsÚ
showscopesÚshowvariablesÚshowvarsÚ	sreadmembÚ	sreadmemhÚstimeÚstopÚstrobeÚtimeÚ
timeformatÚwritez\$)ÚbyteÚshortintÚintÚlongintr[   ræ   ÚbitÚlogicÚregÚsupply0Úsupply1ÚtriÚtriandÚtriorÚtri0Útri1ÚtriregÚuwireÚwireÚwandÚworshortrealÚrealrÓ   ú[a-zA-Z_]\w*:(?!:)ú\$?[a-zA-Z_]\w*ú\\(\S+)ú"ú#popú/\\([\\abfnrtv"\']|x[a-fA-F0-9]{2,4}|[0-7]{1,3})ú	[^\\"\n]+ú\\ú[^/\n]+ú/[*](.|\n)*?[*]/z//.*?\nú/ú	(?<=\\)\nú\nú	[\w:]+\*?©Úrootr   r   r'   c                 C   s8   d}d| v r
|d7 }d| v r|d7 }d| v r|d7 }|S )z`Verilog code will use one of reg/wire/assign for sure, and that
        is not common elsewhere.r   rï   gš™™™™™¹?rù   r-   © )ÚtextÚresultr  r  úP/var/www/html/CropPilot/venv/lib/python3.10/site-packages/pygments/lexers/hdl.pyÚanalyse_text„   s   zVerilogLexer.analyse_textN)'Ú__name__Ú
__module__Ú__qualname__Ú__doc__ÚnameÚaliasesÚ	filenamesÚ	mimetypesÚurlÚversion_addedÚ_wsr	   ÚPreprocr   r   r   ÚEscapeÚSingleÚ	Multiliner   ÚCharr   ÚFloatÚHexÚBinÚIntegerÚOctr
   r   ÚConstantr   Ú	Namespacer   r   ÚBuiltinÚTypeÚLabelÚtokensr  r  r  r  r  r      s’    
ÿïîùø
	÷
öüûµNû
ú
	ÿ£br   c                
   @   sD  e Zd ZdZdZddgZddgZdgZdZdZ	d	Z
g d
eeejƒdf‘deeejeƒf‘deeejeƒdf‘def‘deejeƒf‘dejf‘dejf‘def‘dedf‘dejf‘dejf‘dejf‘dejf‘dejf‘dejf‘dejf‘def‘dejf‘def‘ed d!d"�ejf‘d#ef‘d$e j!f‘ed%d!d"�ef‘d&eej"ee j#ƒf‘d'eej"ee j#ƒf‘d(eej"eeee j#ƒf‘ed)d!d"�ej$f‘ed*d!d"�ejf‘ed+d!d"�e j%f‘d,e j&f‘d-e f‘d.e f‘d/ed0fd1ejfd2efdeejeƒfd3efgd4ejfd5ejfd6ejd0fd7ejfd8ejfd9ed0fgd:e jd0fgd;œZ'd<S )=r   zi
    Extends verilog lexer to recognise all SystemVerilog keywords from IEEE
    1800-2009 standard.
    ÚsystemverilogÚsvz*.svz*.svhztext/x-systemverilogz+https://en.wikipedia.org/wiki/SystemVerilogú1.5r   z^(\s*)(`define)r   r%   r&   r'   r   r   r   r   r   r   r   r   r    r!   z4([1-9][_0-9]*)?\s*\'[sS]?[bB]\s*[xXzZ?01][_xXzZ?01]*z6([1-9][_0-9]*)?\s*\'[sS]?[oO]\s*[xXzZ?0-7][_xXzZ?0-7]*z6([1-9][_0-9]*)?\s*\'[sS]?[dD]\s*[xXzZ?0-9][_xXzZ?0-9]*zB([1-9][_0-9]*)?\s*\'[sS]?[hH]\s*[xXzZ?0-9a-fA-F][_xXzZ?0-9a-fA-F]*z
\'[01xXzZ]z[0-9][_0-9]*r"   )ÚinsideÚdistr˜   r™   z[()\[\],.;\'$]r$   )ÒÚ	accept_onÚaliasr(   r)   r*   r+   r,   Úassertr-   Úassumer.   Úbeforer/   ÚbindÚbinsÚbinsofr0   r1   r2   r3   r4   r5   r6   ÚcellÚcheckerÚclockingr7   ÚconfigÚ
constraintÚcontextr9   ÚcoverÚ
covergroupÚ
coverpointÚcrossr:   r;   r<   Údesignr=   r>   r?   r@   rA   rB   Ú
endcheckerÚendclockingÚ	endconfigrC   rD   ÚendgroupÚendinterfacerE   rF   rG   Ú
endprogramÚendpropertyÚendsequencerH   rI   rJ   rK   Ú
eventuallyÚexpectÚexportÚexternrM   Úfirst_matchrN   rO   ÚforeachrP   rQ   ÚforkjoinrR   rS   rT   ÚglobalrU   rV   rW   ÚiffÚifnoneÚignore_binsÚillegal_binsÚimpliesÚ
implementsr'   Úincdirr   rX   rY   rZ   ÚinstanceÚinterconnectÚ	interfaceÚ	intersectr\   Újoin_anyÚ	join_noner]   ÚletÚliblistÚlibraryÚlocalr^   r_   Úmatchesr`   Úmodportra   rb   rc   ÚnettypeÚnewÚnexttimerd   re   Únoshowcancelledrf   rg   rh   Únullri   rj   Úpackagerk   rl   rm   rn   ro   ÚpriorityÚprogramÚpropertyr­   rp   rq   rr   rs   Úpulsestyle_ondetectÚpulsestyle_oneventÚpureÚrandÚrandcÚrandcaseÚrandsequencert   ru   Ú	reject_onrv   rw   Úrestrictrx   ry   rz   r{   r|   r}   Ús_alwaysÚs_eventuallyÚ
s_nexttimeÚs_untilÚs_until_withr~   ÚsequenceÚshowcancelledr€   ÚsoftÚsolver�   r‚   ÚstaticÚstrongr„   r…   r†   ÚsuperÚsync_accept_onÚsync_reject_onr‡   Útaggedrˆ   r   Ú
throughoutÚtimeprecisionÚtimeunitr‰   rŠ   r‹   r�   ÚunionÚuniqueÚunique0ÚuntilÚ
until_withÚuntypedÚuser�   Úvirtualr’   Ú
wait_orderÚweakr“   r”   r•   ÚwildcardÚwithÚwithinr–   r—   z(class)(\s+)([a-zA-Z_]\w*)z(extends)(\s+)([a-zA-Z_]\w*)z,(endclass\b)(?:(\s*)(:)(\s*)([a-zA-Z_]\w*))?)!rí   ré   Úchandler8   rL   rë   r[   rî   rì   rü   rÓ   rï   rê   Ú	shortrealr   r   ræ   rŒ   rŽ   r�   r‘   rð   rñ   rò   ró   rô   r÷   rõ   rö   rø   rú   rù   Úwor)z	`__FILE__z	`__LINE__z`begin_keywordsz`celldefinez`default_nettypez`definez`elsez`elsifz`end_keywordsz`endcelldefinez`endifz`ifdefz`ifndefz`includez`linez`nounconnected_drivez`pragmaz	`resetallz
`timescalez`unconnected_drivez`undefz`undefineall)Äz$exitz$finishz$stopz	$realtimez$stimez$timez$printtimescalez$timeformatz$bitstorealz$bitstoshortrealz$castz$itorz$realtobitsz$rtoiz$shortrealtobitsz$signedz	$unsignedz$bitsz$isunboundedz	$typenamez$dimensionsz$highz
$incrementz$leftz$lowz$rightz$sizez$unpacked_dimensionsz$acosz$acoshz$asinz$asinhz$atanz$atan2z$atanhz$ceilz$clog2z$cosz$coshz$expz$floorz$hypotz$lnz$log10z$powz$sinz$sinhz$sqrtz$tanz$tanhz
$countbitsz
$countonesz
$isunknownz$onehotz$onehot0z$infoz$errorz$fatalz$warningz$assertcontrolz$assertfailoffz$assertfailonz$assertkillz$assertnonvacuousonz
$assertoffz	$assertonz$assertpassoffz$assertpassonz$assertvacuousoffz$changedz$changed_gclkz$changing_gclkz$falling_gclkz$fellz
$fell_gclkz$future_gclkz$pastz
$past_gclkz$rising_gclkz$rosez
$rose_gclkz$sampledz$stablez$stable_gclkz$steady_gclkz$coverage_controlz$coverage_getz$coverage_get_maxz$coverage_mergez$coverage_savez$get_coveragez$load_coverage_dbz$set_coverage_db_namez$dist_chi_squarez$dist_erlangz$dist_exponentialz$dist_normalz$dist_poissonz$dist_tz$dist_uniformz$randomz$q_addz$q_examz$q_fullz$q_initializez	$q_removez$async$and$arrayz$async$and$planez$async$nand$arrayz$async$nand$planez$async$nor$arrayz$async$nor$planez$async$or$arrayz$async$or$planez$sync$and$arrayz$sync$and$planez$sync$nand$arrayz$sync$nand$planez$sync$nor$arrayz$sync$nor$planez$sync$or$arrayz$sync$or$planez$systemz$displayz	$displaybz	$displayhz	$displayoz$monitorz	$monitorbz	$monitorhz	$monitoroz$monitoroffz
$monitoronz$strobez$strobebz$strobehz$strobeoz$writez$writebz$writehz$writeoz$fclosez	$fdisplayz
$fdisplaybz
$fdisplayhz
$fdisplayoz$feofz$ferrorz$fflushz$fgetcz$fgetsz	$fmonitorz
$fmonitorbz
$fmonitorhz
$fmonitoroz$fopenz$freadz$fscanfz$fseekz$fstrobez	$fstrobebz	$fstrobehz	$fstrobeoz$ftellz$fwritez$fwritebz$fwritehz$fwriteoz$rewindz$sformatz	$sformatfz$sscanfz$swritez$swritebz$swritehz$swriteoz$ungetcz	$readmembz	$readmemhz
$writemembz
$writememhz$test$plusargsz$value$plusargsz$dumpallz	$dumpfilez
$dumpflushz
$dumplimitz$dumpoffz$dumponz
$dumpportsz$dumpportsallz$dumpportsflushz$dumpportslimitz$dumpportsoffz$dumpportsonz	$dumpvarsrý   rþ   rÿ   r   r  r  r  r  r  r  z//.*?$r  r  r	  r
  r  N)(r  r  r  r  r  r  r  r  r  r  r  r   r   r	   r  r   r(  r   r  r  r   r   r!  r   r"  r$  r&  r%  r#  r
   r   ÚWordr   r'  ÚDeclarationÚClassr*  r)  r+  r,  r  r  r  r  r   ’   s    ÿþýûúùø	÷
öõóòÿðÿîÿìÿêçæäãá à")×*ÖÞNÿ²Pÿ°Rÿ®U	÷
ö«aúùŸjM³N²– ; �Å < �Ä = �Ã @û
ú
	ÿ �
±r   c                   @   sÆ  e Zd ZdZdZdgZddgZdgZdZdZ	e
je
jB Zdefd	eejeƒfd
ejfdejfdejfdefdejfdefdefdeeeejƒfdeeeeƒfdeeeejeƒfdeeeejƒfdeejejƒfeddd�ejfdeeeejƒfdeeeejeeeejeeƒ	fdeejeeeƒfdeeeƒeƒdfe dƒe dƒe d ƒd!efge dƒd!ejfdefd"ed#fged$dd�ej!fged%dd�efgd&e"j#fd'e"j#fd(e"j$fd)e"j%fd*e"j&fd+e"j'fgd,œZ(d-S ).r   z
    For VHDL source code.
    Úvhdlz*.vhdlz*.vhdztext/x-vhdlz"https://en.wikipedia.org/wiki/VHDLr/  r   r   z--.*?$r   z'(U|X|0|1|Z|W|L|H|-)'r"   z
'[a-z_]\w*r#   z"[^\n\\"]*"z(library)(\s+)([a-z_]\w*)z(use)(\s+)(entity)z(use)(\s+)([a-z_][\w.]*\.)(all)z(use)(\s+)([a-z_][\w.]*)z(std|ieee)(\.[a-z_]\w*))ÚstdÚieeeÚworkr˜   r™   z"(entity|component)(\s+)([a-z_]\w*)zN(architecture|configuration)(\s+)([a-z_]\w*)(\s+)(of)(\s+)([a-z_]\w*)(\s+)(is)z ([a-z_]\w*)(:)(\s+)(process|for)z
(end)(\s+)ÚendblockÚtypesÚkeywordsÚnumbersz	[a-z_]\w*ú;r  )Úbooleanrí   Ú	characterÚseverity_levelr[   ræ   Údelay_lengthÚnaturalÚpositiver   Ú
bit_vectorÚfile_open_kindÚfile_open_statusÚ
std_ulogicÚstd_ulogic_vectorÚ	std_logicÚstd_logic_vectorr   rŽ   )_ÚabsÚaccessÚafterr3  Úallr,   ÚarchitectureÚarrayr4  Ú	attributer/   ÚblockÚbodyÚbufferÚbusr4   Ú	componentÚconfigurationÚconstantÚ
disconnectÚdowntor@   rŸ   rA   ÚentityÚexitÚfilerN   rR   rS   ÚgenericÚgroupÚguardedrW   ÚimpureÚinÚinertialrY   ÚisÚlabelrd  ÚlinkageÚliteralÚloopÚmapÚmodrb   ri  Únextre   rf   rl  ÚofÚonÚopenri   ÚothersÚoutrm  ÚportÚ	postponedÚ	procedureÚprocessrs  ÚrangeÚrecordÚregisterÚrejectÚremrx   ÚrolÚrorÚselectÚseverityÚsignalÚsharedÚslaÚsllÚsraÚsrlÚsubtypeÚthenÚtoÚ	transportrŒ   Úunitsr�  r’  Úvariabler’   Úwhenr•   r—  r–   r—   z\d{1,2}#[0-9a-f_]+#?z\d+z(\d+\.\d*|\.\d+|\d+)E[+-]?\d+zX"[0-9a-f_]+"z
O"[0-7_]+"z	B"[01_]+")r  r£  r¤  r¥  r¦  N))r  r  r  r  r  r  r  r  r  r  ÚreÚ	MULTILINEÚ
IGNORECASEÚflagsr   r   r   r  r	   r  r   r!  r
   r   Ú	Attributer   r   r(  r   rž  r   r   r   r*  r   r%  r"  r#  r&  r$  r,  r  r  r  r  r   u  s˜    ÿÿÿÿ
ÿÿÿþÿÜ'üüûÿ	ðïÿú
·r   )r  rõ  Úpygments.lexerr   r   r   r   r   r   Úpygments.tokenr   r	   r
   r   r   r   r   r   r   Ú__all__r   r   r   r  r  r  r  Ú<module>   s    
 ,~ d